1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a non-volatile memory and manufacturing and operating method thereof.
2. Description of the Related Art
Among the various types of non-volatile memory products, electrically erasable programmable read only memory (EEPROM) is a memory device that has been widely used inside most personal computer systems and electronic equipment. In an EEPROM, data can be stored, read out or erased from the EEPROM numerous times and any stored data is retained even after power is cut off.
Typically, the floating gate and the control gate of an EEPROM cell is fabricated using doped polysilicon. To prevent errors in reading data from an EEPROM due to over-erasing, a select gate is disposed on the sidewalls of the control gate and the floating gate above the substrate, thereby forming a split-gate structure.
On the other hand, because doped polysilicon is used to fabricate the floating gates, any defects in the tunneling oxide layer under the floating gate can easily produce a leakage current and affect the reliability in the device.
To resolve the current leakage problem in the EEPROM, a charge-trapping layer often replaces the conventional polysilicon floating gate of the memory. The charge-trapping layer is fabricated using silicon nitride, for example. In general, an oxide layer is formed both above and below the silicon nitride charge-trapping layer to form a stacked structure including an oxide-nitride-oxide (ONO) composite layer. Read-only memory having this type of stacked gate structure is often referred to as a silicon-oxide-nitride-oxide-silicon (SONOS) memory device.
At present, an AND type memory array structure, constructed using split-gate memory cells with ONO structure, is disclosed in U.S. Patent application US2004/0084714. FIG. 1 is a schematic cross-sectional view of a conventional AND type memory cell structure. As shown in FIG. 1, the memory cell has a triple-well structure composed of a p-type silicon substrate 16, an n-type well 15 and a p-type well 14. A plurality of n-type diffusion layers 2, 3, 6 and 7 are disposed within the p-type well 14. A plurality of assist electrodes 4, 8 and 9 are disposed on the substrate. A gate oxide layer 18 is disposed between assist electrodes 4, 8 and 9 and the substrate. A control electrode 5 is disposed on the substrate to serve as a word line. A silicon oxide layer 19, a silicon nitride layer 17, and a silicon oxide layer 20 are sequentially laid between the control gate and the substrate and between the control gate 5 and the assist electrodes 4, 8, 9. The silicon nitride layer 17 between the assist electrode 4 and its adjacent n-type diffusion layers 2, 3 are divided into two charge-trapping regions 10 and 11. When a voltage is applied to the assist electrode 4, an inversion layer 1 is formed in the surface of the substrate under the assist electrode 4.
With the trend toward increasing the level of integration of integrated circuits and miniaturizing electronic devices, the size of the aforementioned AND type memory cell needs to be reduced. One way of shrinking the AND type memory cell is to reduce the length of the assist electrode and minimize the distance separating the n-type diffusion layers 2, 3, 6, 7 and the assist electrodes 4, 8, 9. However, shortening the length of the assist electrodes 4, 8, 9 and minimizing the distance between the n-type diffusion layers 2, 3, 6, 7 and the assist electrodes 4, 8, 9 bring the n-type diffusion layer 2, 3, 6, 7 closer together. As a result, abnormal electrical punch-through of the channel underneath the memory cell occurs with higher frequency. To prevent the n-type diffusion layers 2, 3, 6 and 7 from getting too close to cause the channel underneath the memory cell to conduct, the n-type diffusion layers 2, 3, 6, 7 must be separated from each other by a minimum distance, and as a result, the dimension of each memory cell cannot be further minimized.